64-bit and Multimedia Extensions in the PA-RISC 2.0 Architecture

This paper describes the architectural extensions to the PA-RISC 1.1 architecture to enable 64-bit processing of integers and pointers. It also describes MAX, the Multi-media Acceleration eXtensions which speed up the processing of multimedia and other applications with parallelism at the intra instruction, or subword, level. Other additions to the PA-RISC 2.0 architecture include performance enhancements with respect to memory hierarchy management, branch penalty reduction, and floating-point performance. When the original PA-RISC 1.0 Architecture was designed in the early eighties, its goal was to be a single architecture that efficiently spans Hewlett-Packard's three computer lines: the HP3000 commercial minicomputers, the HP9000 technical workstations and servers, and the HP1000 realtime controllers. Before introduction, the program was codenamed SPECTRUM. At introduction in 1986, it was known as HP's Precision Architecture [1,2], HP-PA, or just PA. Subsequently, the architecture was called PA-RISC, with the first version of the architecture known as PA-RISC 1.0. Since its introduction, the PA-RISC architecture has remained remarkably stable. Only minor changes were made over the next decade, to facilitate higher performance in floating-point and system processing. When PA-RISC 1.0 was designed, floating-point performance was not essential for the majority of the HP computer systems targeted at that time. Hence, the architecture defined floating-point support as optional coprocessor instructions , without emphasizing high performance. In 1989, driven by the performance needs of the HP9000 technical workstation line, PA-RISC 1.1 was introduced. This included additional floating-point capabilities, such as more floating-point registers, doubling the amount of register space for single-precision floating-point numbers, and introducing combined operation floating-point instructions[3]. These floating-point features enabled higher performance in technical computations, including graphics, where single-precision floating-point numbers are extensively used. In the system area, PA-RISC 1.1 architectural extensions were made to speed up the processing of performance-sensitive abnormal events, such as misses in the address translation cache (also called the TLB). Such architectural changes are only visible to the operating system, and do not affect any applications programs. Minor system changes have been added to the three editions of the PA-RISC 1.1 architecture, known as editions 1, 2 and 3, respectively, of the architecture manual [3,4,5]. PA-RISC 1.1 also added bi-endian support. Previously , PA-RISC 1.0 was a consistently big endian machine , but in PA-RISC 1.1, support for little endian was also provided by means of a mode bit. The PA-RISC 2.0 architecture represents the first time that user-visible changes have been made …